Sunday, June 23, 2024
12:00 -13:05
Short Course 1: Prof. Daniele Ielmini
Chair: Nazek El-Atab
13:05 - 13:15
Coffee Break
13:15 - 14:20
Short Course 2: Dr. Abu Sebastian
Chair: Nazek El-Atab
14:20 - 14:30
Coffee Break
14:30 - 15:35
Short Course 3: Prof. Hussam Amrouch
Chair: Thomas Kampfe
15:35 - 15:45
Coffee Break
15:45 - 16:50
Short Course 4: Prof. Giuseppe Iannaccone
Chair: Saroj Dash
Abstract: In the burgeoning realm of artificial intelligence (AI), the pursuit of In-Memory Computing (IMC) is paramount. This relentless pursuit, aimed at catalyzing ultra-fast and energy-efficient AI computations, is emblematic of the cutting-edge innovations at the nexus of Ferroelectric FET (FeFET) technology. In this short course, we will showcase the latest advancements in FeFETs, spanning from traditional IMC-based hardware accelerators to monolithic 3D integration using advanced back-end-of-line (BEOL) thin-film transistors. We will elucidate the inherent challenges posed by ferroelectric stochasticity along with temperature effects, and demonstrate innovative strategies, such as using thermoelectric devices for advanced on-chip cooling, to mitigate their adverse impacts, paving the way for reliable computing using FeFET-based IMC. Finally, we will demonstrate the synergy between IMC and brain-inspired hyperdimensional computing and how technology/algorithm co-optimization is the key to realize reliable in-memory computing using FeFET devices.
Bio: Hussam Amrouch is a Professor heading the Chair of AI Processor Design at the Technical University of Munich (TUM). He is, additionally, heading the Brain-inspired Computing at the Munich Institute of Robotics and Machine Intelligence. Further, he is the head of the Semiconductor Test and Reliability at the University of Stuttgart. He received his Ph.D. degree with the distinction (summa cum laude) from KIT, Germany in 2015. He has more than 260 publications (including over 110 articles in many top journals like Nature Communications) in multidisciplinary research areas covering semiconductor device physics, circuit design and computer architecture. His research interest is transistor compact modeling, in-memory computing with a special focus on reliability, and cryogenic circuits for quantum computing.
Abstract: In this talk we will discuss the main requirements of devices for neuromorphic computing and the impact of device properties on the operation of deep neural networks and on the performance figures of merit at the system level, such as classification accuracy, scalability to large models, energy per classification, throughput. These considerations enable us to analyze and compare different materials and device options for neuromorphic systems, including hybrid integration, and to evaluate the impact of the expected progress of materials, device, and technology roadmaps.
Bio: Giuseppe Iannaccone (Fellow, IEEE) received the M.S. and Ph.D. degrees in EE from the University of Pisa, in 1992 and 1996, respectively. He is currently Professor of electronics and Deputy President at the University of Pisa, Italy. He has coordinated several European and national projects involving multiple partners and has acted as a principal investigator of several research projects funded by public agencies at the European and national level, and by private organizations. He is also active in academic entrepreneurship through Quantavis s.r.l. and other technology transfer initiatives. He has authored or coauthored more than 270 articles published in peer-reviewed journals and more than 160 papers in proceedings of international conferences, gathering more than 10K citations on the Scopus database. His research interests include quantum transport and noise in nanoelectronic and mesoscopic devices, the development of device modeling tools, new device concepts and circuits beyond CMOS technology for artificial intelligence, cybersecurity, implantable biomedical sensors, and the Internet of Things. He is a fellow of the American Physical Society.
Abstract: Artificial neural networks (ANNs) had their algorithmic roots in computational neuroscience. However, their contemporary development is primarily driven by computer scientists and engineers, leading to an astonishing rate of evolution. A significant challenge facing the field lies in meeting the computational and energy demands of ANNs.
It's becoming increasingly evident that brain-inspired approaches are essential also for shaping the next generation of computing substrates for ANNs. One such approach involves creating physically static synaptic elements using nanoscale memory components and executing some processing tasks in the analog domain. Phase-change memory (PCM) emerges as particularly suitable for this method, known as "in-memory computing". Recent demonstrations utilizing advanced prototype chips illustrate the effectiveness of this strategy.
This short course will offer a comprehensive overview of the field, with a focus on device-level considerations. Additionally, it will delve into an ongoing effort aimed at designing embedded neural processing units based on PCM devices. Furthermore, it will briefly touch upon ANN training and explore the potential of more biologically realistic ANNs leveraging additional PCM device physics.
Dr. Abu Sebastian is a Distinguished Scientist and technical manager at IBM Research – Zurich. He is one of the technical leaders of IBM’s research efforts towards next generation AI Hardware and manages the in-memory computing group at IBM Research - Zurich. He is the author of over 200 publications in peer-reviewed journals/conference proceedings and holds over 90 US patents. In 2015 he was awarded the European Research Council (ERC) consolidator grant and in 2020, he was awarded an ERC Proof-of-concept grant. He was an IBM Master Inventor and was named Principal and Distinguished Research Staff Member in 2018 and 2020, respectively. In 2019, he received the Ovshinsky Lectureship Award for his contributions to "Phase-change materials for cognitive computing". In 2023, he was conferred the title of Visiting Professor in Materials by University of Oxford. He is a distinguished lecturer and fellow of the IEEE.
Abstract: Neuromorphic computing is a novel paradigm for information processing at low energy consumption thanks to brain inspired analog and event-driven methodologies. To minimize the cost and energy of neuromorphic chips, memory devices are most beneficial, thanks to their capability to replicate neuron and synapse behavior at the nanoscale. A number of applications has emerged, including in-memory matrix-vector multiplication (MVM) for inference and training of deep neural networks (DNNs), short- and long-term synaptic plasticity, leaky integrate-and-fire (LIF) neurons for spiking neural networks (SNNs) and reservoir computing (RC). However, each of these applications have specific and sometimes diverging requirements at the device level.
This short course will provide an overview of the applications and requirements of devices for neuromorphic computing, addressing a broad range of emerging memory and materials, such as resistive switching memory (RRAM) and 2D semiconductors. The device requirements in terms of conductance range, linearity of conduction, linearity of potentiation/depression, temperature stability, stochastic variation, time constants of short-term memory, scaling and CMOS compatibility will be discussed and benchmarked. Finally, new figures of merit will be proposed for a fair comparison and assessment of memory devices for neuromorphic computing.
Bio: Daniele Ielmini is a Full Professor at the Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Italy. He received the Ph.D. from Politecnico di Milano in 2000. He held visiting positions at Intel Corporation (2006), Stanford University (2006) and the University of Illinois at Urbana-Champaign (2010). His research interests include non-volatile memories, such as phase change memory (PCM), resistive switching memory (RRAM), and spin-transfer torque magnetic memory (STT-MRAM), and novel in-memory computing circuits. He authored/coauthored 15 book chapters, more than 400 papers published in international journals and presented at international conferences, and 8 patents. He is Associate Editor of IEEE Trans. Nanotechnology and Semiconductor Science and Technology. He received the Intel Outstanding Researcher Award, the Ovshinsky Award, the IEEE-EDS Paul Rappaport Award, the ERC Consolidator Grant and the ERC Advanced Grant. He is a Fellow of the IEEE.
